1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a MOS-gate power semiconductor device.
2. Description of the Related Art
Semiconductor devices such as an insulated gate bipolar transistor (IGBT) and a metal-oxide semiconductor field effect transistor (MOSFET) are mainly used as switching devices in the field of power electronic applications. That is, the semiconductor devices are used as semiconductor switching devices in the power electronic applications such as an H-bridge inverter, a half-bridge inverter, a 3-phase inverter, a multi-level inverter, and a converter.
However, in power electronic circuits including the semiconductor switching devices (that is, semiconductor devices used as the semiconductor switching devices), the semiconductor switching devices may happen to be deteriorated or destructed by the overcurrent flow due to a malfunction of driving circuitry. Accordingly, it is necessary to avoid such failures due to the overcurrent and moreover to prevent the deterioration and/or destruction of the semiconductor switching devices.
Hereinafter, operations of an H-bridge inverter circuit employing the semiconductor switching devices will be described along with a shoot-through phenomenon as an example of the failure in the circuit.
FIGS. 1A and 1B are a circuit diagram illustrating the H-bridge inverter circuit employing the IGBT and a graph illustrating its gate voltage and load voltage characteristics, respectively.
As shown in FIG. 1A, the H-bridge inverter circuit includes four semiconductor switching devices M1 to M4 and a load 120 connected to an output node 110 between the semiconductor switching devices. The IGBTs are shown as the semiconductor switching devices in FIG. 1A, but semiconductor switching devices such as MOSFETs may be also employed.
The semiconductor switching devices M1 to M4 included in the H-bridge inverter circuit are alternately turned on and off in a switching sequence to supply AC power to the load 120 connected to the output node 110 between the semiconductor switching devices. Here, each pair of semiconductor switching devices is called arm or leg.
When the semiconductor switching devices M1 and M3 are turned on and the semiconductor switching devices M2 and M4 are turned off under the control of a driving circuit for the semiconductor switching devices, a current flows in the direction of A. On the contrary, when the semiconductor switching devices M2 and M4 are turned on and the semiconductor switching devices M1 and M3 are turned off, the current flows in the direction of B.
Accordingly, as shown in FIG. 1B, when the semiconductor switching devices M1 and M3 are maintained in the ON state for a half of a switching period T and the semiconductor switching devices M2 and M4 are maintained in the ON state for the other half of the switching period T, the output voltage to the load 120 has a shape of AC voltage of which the polarity varies. In this way, when the turning-on/off operations of the semiconductor switching devices are normally controlled by the driving circuit, the current in the direction of A or B flows into the load.
Therefore, it is indispensable to control the semiconductor switching devices M1 and M4 (or M2 and M3) disposed in the same arm not to simultaneously be in the ON state. As shown in FIG. 1B, the semiconductor switching devices are controlled to have a dead time between the turning-off of M1 and the turning-on of M4 or between the turning-off of M4 and the turning-on of M1 (which is true in M2 and M3).
Otherwise, a short circuit is formed between the semiconductor switching devices disposed in the same aim to cause the shoot-through phenomenon, when the semiconductor switching devices disposed in the same arm are simultaneously in the ON state. That is, a very large short circuit current flows through the formed short circuit, which causes the deterioration and/or destruction of the semiconductor switching devices.
FIG. 2 is a plan view illustrating a known semiconductor switching device and FIG. 3 is a sectional view taken along line a-b of FIG. 2.
Referring to FIGS. 2 and 3, a semiconductor substrate 200 formed of silicon has a top surface and a bottom surface opposed to each other. A gate pad electrode 210, an active area 220 including plural cells allowing a current to flow, and an edge termination area 230 supporting a high withstand voltage are formed in the top surface. A collector metal electrode 310 is formed in the bottom surface. Unit cells including a gate poly electrode and an emitter metal electrode are arranged in the active area 220. A gate bus line 240 electrically connected to a gate pad to transmit a gate signal extends around the active area 220 from the gate pad electrode 210. For example, the gate bus line 240 can be formed in a closed loop, but the pattern is not limited to the closed loop. In this specification, an area having the gate pad electrode 210 formed therein is included as an area in the active area 220.
Referring to FIG. 3 showing a sectional view taken along line a-b of FIG. 2, when the semiconductor switching device is an IGBT, plural P-type wells 320 and 322 are formed in an N-type semiconductor substrate 315 and N-type wells 325 are selectively formed in the P-type wells 322. The P-type well 322 forms an active cell along with a gate oxide film 330 and a gate poly electrode 335. A channel can be formed in the P-type well 322, allowing a current to flow by connecting the semiconductor substrate 315 to the N-type well 325, when a gate voltage having a predetermined level is applied to a gate metal electrode 210. An insulating interlayer 340 is formed to include the gate poly electrode 335 therein and an emitter metal electrode 345 including active cells is formed thereon. A collector region 350 is formed under the N-type semiconductor substrate 315 and a collector metal electrode 310 is formed under the collector region 350 by a bottom metal process. The collector region 350 is formed in a P type in case of the IGBT, and is formed in an N type as a drain region in case of the MOSFET.
When the semiconductor device shown in FIG. 3 is the semiconductor switching device M4 shown in FIG. 1A, the collector metal electrode 310 is electrically connected to the output node 110 and the emitter metal electrode 345 is electrically connected to a—terminal of an input voltage. Accordingly, when the semiconductor switching device is in the ON state, the current flows from the output node 110 to the—terminal of the input voltage.
In an abnormal state such as the above-mentioned shoot-through phenomenon, an overcurrent flows to the outside via the emitter metal electrode 345, which can cause the deterioration and/or destruction of the semiconductor switching device.
To prevent the shoot-through phenomenon, the semiconductor devices are controlled with the dead time. However, the possibility that the shoot-through phenomenon occurs cannot be completely excluded in various abnormal states where the control sequence of the driving circuit is not normally designed or the driving circuit for the semiconductor switching devices operates erroneously.
Particularly, since a tail current exists due to the characteristic of the IGBT, a sufficient dead time is required for preventing the shoot-through phenomenon. However, the elongation of the dead time causes an increase in harmonics due to the distortion in output waveform of an inverter, thereby lowering the performance of the inverter.
Therefore, there is a need for developing a semiconductor switching device which can protect a circuit and the semiconductor switching device itself in an abnormal state such as the shoot-through phenomenon.
The above-mentioned background art is technical information thought out to make the invention or learned in the course of making the invention by the inventor, and cannot be thus said to be technical information known to the public before filing the invention.